A phase-locked loop (PLL) is a linear control system that operates by producing an oscillator frequency and phase to match those of a reference input signal. In the locked state, any change in the reference input signal first appears as a change in phase between the reference input signal and the oscillator frequency. This phase shift functions as an error signal to change the phase and frequency of the PLL oscillator. Phase-locked loops may be used in a wide range of applications and may realize a variety of functions. Exemplary functions for which PLLs may be used to accomplish include clock extraction, clock recovery, clock synchronization, carrier recovery, tracking filters, frequency synthesis, frequency and phase demodulation, phase modulation and numerous other functions.
A basic PLL may comprise a phase detector (PD), a voltage-controlled oscillator (VCO), a feedback interconnection and a loop filter. The phase detector is typically a non-linear device that, over a limited range, creates a linear output signal that corresponds to the phase difference between two periodic input signals: a reference signal and a feedback signal provided by a feedback interconnection. The voltage-controlled oscillator produces a periodic signal whose frequency is controlled by an input voltage with preferably a linear transfer function of voltage to frequency. Since frequency as function of time is the time-rate-of-change (time-derivative) of phase as a function of time, the phase of the VCO periodic output signal relative to a reference phase will be proportional to the time-integral of the input voltage. The constant of proportionality is the VCO gain with units of, for example, radians/volt-sec. In other words, the VCO accumulates phase (radians) proportional to the area (volts times seconds) under the voltage versus time input. Therefore, a PLL that contains a VCO rather than a simple phase modulator has at least one integrator in the control loop due to the VCO.
While the loop filter may be omitted, it is typically required in order for the PLL to function properly. In particular, it is needed when more than one integrator is used in the loop.
Two terms, type and order, may be used to describe a PLL. The type of a PLL system refers to the number of poles of the open-loop transfer function that are located at the origin. This also corresponds to the number of true integrators within the feedback loop. The order of a PLL system refers to the highest degree of the polynomial expression referred to as the characteristic equation.
In some applications, a Type-II phase-locked loop may be advantageous since the two integrators requisite for a Type-II classification effectuate removal of the static phase error for any frequency-offset. A Type-III phase-locked loop additionally removes any phase error for an input signal that is linearly changing with frequency over time.
In some applications, a Type-III phase-locked loop may be required to meet design and measurement specifications. In an exemplary application described in IEEE Standard 1521-20031, “IEEE Trial-Use Standard for Measurement of Video Jitter and Wander,” which is hereby incorporated by reference herein in its entirety, a Type-III feedback control phase-locked loop is suggested for measuring jitter using an extracted clock to trigger an oscilloscope. In this application, at least one analog VCO is desired to provide the periodic signal to trigger the oscilloscope. Two phase-locked loops, one of Type-II and the other of Type-I, may be cascaded to provide the requisite Type-III response in the cited standard but this is expensive so a single PLL is preferred. The PLL may be a hybrid of analog and digital signal processing using DAC and/or ADC converters, but would have an output from the VCO to provide oscilloscope trigger with a Type-III phase tracking response.
A single, analog Type-III PLL is preferable over the higher cost and power consumption of the analog/digital hybrid or two cascaded phase-locked loops. However, Type-III phase-locked loops are often described in the literature as inherently unstable or impossible to realize. In fact, while the IEEE Standard 1521-20031 suggests the Type-III phase-locked loop for measuring jitter using an extracted clock to trigger an oscilloscope, this document does not describe or teach an analog, or hybrid digital/analog, Type-III phase-locked loop design, nor does it teach the use of the cascade of two phase-locked loops.
Other design specifications and standards (for example, SMPTE RP 192-2003, “PROPOSED SMPTE RECOMMENDED PRACTICE Jitter Measurement Procedures in Bit-Serial Digital Interfaces”) also expect a Type-III phase-locked loop response. However these documents neither teach nor enable the Type-III phase-locked loop. In fact, many of the references specifically state the difficulty, often state the impossibility, of realizing a single, stable, analog Type-III phase-locked loop. Typically these references further suggest less difficult to implement alternatives to the preferred Type-III loop, for example, a Type-II phase-locked loop.
A single, stable, realizable, analog Type-III phase-locked loop is desirable.